There continues to be demand for increasingly higher speed electronic components housed in yet smaller and smaller device packages. Smaller device packages translate into greater convenience to a consumer for obvious reasons. One way component manufacturers meet such demands for smaller device packages is by shrinking semiconductor chip geometries and/or increasing the chip's corresponding functionality. As a result of this trend toward smaller packaging and overall chip size, chip device designs (as well as other types of electronic components) are becoming increasingly susceptible to damage by Electrostatic Discharge (ESD). In general, an ESD pulse is a short duration, high-amplitude voltage pulse causing a burst of current to flow between two objects having different electrostatic potentials. Smaller geometries lower the threshold level of an ESD pulse that a corresponding device can handle without causing at least minor stress damage. Consequently, smaller devices are more susceptible to even minimal ESD pulses.
One potential cause of failure associated with electronic devices exposed to ESD is melting of material due to high temperatures. For example, silicon is a very poor conductor. Therefore, even low levels of quick burst energy pulses can cause the material of a semiconductor device to melt down and be permanently damaged. It is worth noting that not all ESD discharges are instantly fatal; certain events will only weaken the device making it more likely to fail early in its useful life.
Another potential cause of failure associated with ESD events is a phenomenon known as punch-through. As its name suggests, this condition results in structural damage due to a hole being blasted through an oxide layer of a semiconductor device as a result of exposure to excessive electrical fields. This phenomenon may also render the semiconductor device inoperable.
Exposure of ESD pulses to chips, electronic circuit boards, and equipment in general is almost inevitable, which is one reason why ESD is presently the leading cause of device failure in the field. Therefore, protection against ESD is typically a major consideration associated with the design, application and purchase of electronic components and, more particularly, sensitive semiconductor devices. Ensuring that devices provide a reasonable and acceptable level of tolerance with respect to ESD is an important part of all device design and manufacturing programs. To determine the ESD threshold of a device, it is necessary to agree on the type of ESD stress for which testing will take place.
FIG. 1 is a diagram of an electronic circuit 100 illustrating a conventional technique of testing a semiconductor device according to MIL-STD-883E (Military Standard 883E). This standard and corresponding specified circuit simulate ESD according to the Human Body Model (HBM). Other common standards that specify different types of ESD for testing an integrated circuit include the Machine Model (MM) and the Charged Device Model (CDM). Each of these models has an associated specification that defines the circuit components (e.g., resistive, capacitive, and inductive components) to shape the corresponding test waveform. Each of these models also has an associated specification including procedures to be used for testing electronic circuit components.
In general, generation of a simulated HBM or MM ESD pulse according to the standards involves two phases. During a charging phase, switch S1 is set so that conductive throw lead 115 couples node A to node B. Thus, capacitor C1 charges to a voltage produced by high voltage source 110. In a following discharge phase, switch S1 is set so that conductive throw lead 115 couples node B to node C. This causes energy in capacitor C1 to discharge through resistor R2 to the device under test 140. The HBM standards specify the values to be used in the circuit elements R2 and C1.
FIG. 2 is a graph illustrating a comparison of an exponential decay voltage waveform 220 and a simulated ESD test pulse 210 produced by the conventional circuit in FIG. 1. The voltage waveforms are similar except the simulated ESD test pulse 210 generally includes an unwanted residual voltage component 215 (e.g., a 2.5 volt plateau for a duration, T1, of 500 microseconds) superimposed on the exponential decay voltage waveform 220. It should be noted that a magnitude of the residual voltage component 210 may vary depending on a load of device under test 140 that test apparatus 100 drives. Also, relevant standards (e.g., MIL-STD, JEDEC, and ESD Association) specify a test voltage waveform as a current pulse into a short circuit. Characteristics of a produced test voltage pulse may vary depending on presence of non-short-circuit load conditions.